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600 ma, 3 mhz fast transient synchronous s tep-down converter preliminary technical data adp2108 rev. p ra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features 3 mhz fixed frequency operation extremely low iq: 19 :a up to 600 ma output current input voltage 2.3 v to 5.5 v uses tiny multilayer inductors and capacitors current mode architecture for fast load and line transient response 100% duty cycle low-dropout mode internal synchronous rectifier internal compensation internal soft start current overload and thermal shutdown protection 0.1 ? a shutdown supply current 5-ball wlcsp package applications pdas and palmtop computers wireless handsets digital audio, portable media players digital cameras, gps navigation units general description the adp2108 is a high efficiency, low quiescent current step- down dc-to-dc converter in ultrasmall wlcsp package. the total solution only requires three tiny external components. it uses a proprietary high speed current mode, constant frequency pwm control scheme for excellent stability and transient response. to ensure the longest battery life in portable applications, the adp2108 has a power saving, pulse frequency modulation (pfm) mode that reduces the switching frequency under light load conditions. the adp2108 runs from input voltages from 2.3 v to 5.5 v allowing single li+/li? polymer cell, multiple alkaline/nimh cell, pcmcia, and other standard power sources. the adp2108 is available in fixed output voltages of 3.3 v, 3.0 v, 2.5 v, 2.3 v, 1.8 v, 1.5 v, 1.3 v, 1.2 v, 1.1 v, and 1.0v. all versions include internal power switch and synchronous rectifier for minimal external part count and high efficiency. adp2108 has an internal soft start and is internally compensated. during logic controlled shutdown, the input is disconnected from the output and it draws less than 0.1 a from the input source. other key features include under-voltage lockout to prevent deep battery discharge and soft start to prevent input current overshoot at startup. the adp2108 is available in a 5-ball wlcsp. typical diagram figure 1 application circuit for a fixed output voltage adp2108 on sw fb vin pgnd 2.3v - 5.5v 1.0 uh off 4.7 uf 4.7 uf 1.0v - vin en
adp2108 preliminary technical data rev. pra | page 2 of 15 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 function block diagram ................................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 4 thermal resistance ...................................................................... 4 esd caution.................................................................................. 4 pin configuration and function descriptions............................. 5 typical performance characteristics ............................................. 6 theory of operation ........................................................................ 7 control scheme .............................................................................7 pwm operation............................................................................7 pfm operation..............................................................................7 pulse skipping threshold ............................................................8 slope compensation .....................................................................8 product features............................................................................8 applications........................................................................................9 external component selection ...................................................9 pcb layout guidelines.................................................................. 12 evaluation board ............................................................................ 13 outline dimensions ....................................................................... 13 ordering guide .......................................................................... 13 revision history 3/08Crev. 0 initial version
preliminary technical data adp2108 rev. pra | page 3 of 15 specifications v in = v en = 3.6 v @ ta = 25c, unless otherwise noted; c in = c out = 4.7 f, l = 1 h unless otherwise noted; all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc); typical values are at t a = +25c. table 1. parameters conditions min typ max unit input characteristics input voltage range 2.3 5.5 v undervoltage lockout threshold v in rising 2.3 v undervoltage lockout threshold v in falling 2.05 2.15 2.25 v output characteristics output voltage accuracy 1 v in = 3.6 v, i load = 0 ma to 600 ma ?2 +2 % v in = 2.5 v to 5.5 v, i load = 0 ma to 600 ma ?2.5 +2.5 % load regulation v in = 3.6 v, i load = 0 ma to 150 ma, 50 ma to 250 ma, 150 ma to 400 ma, t r /t f = 1 3s 50 mv p-p line regulation v in = 600 mv p-p ac square wave. 200 hz, 12.5% duty, i load = 50 ma 50 mv p-p input current characteristics dc operating current i load = 0 ma, device not switching 19 30 a shutdown current v en = 0 v, 3.6 v (en v in +0.2 v maximum) 0.2 1.0 a feedback characteristics pfm/pwm mode hysteresis difference between mode transition points are measured from increasing load vs. decreasing load 50 ma max output current 600 ma psrr pwm mode, i out = 250 ma (<10 khz sine wave) 40 db lx(switch node)characteristics pfet, v in = v gs = 3.6 v, i sw = 150 ma 415 m sw on resistance nfet, v in = v gs = 3.6 v, i sw = 150 ma 210 m sw leakage current v en = 0 v, 3.6 v (en v in + 0.2 v maximum) 1 a current limit 2 switch peak current limit (open-loop) 930 1100 1200 ma minimum on time v in = 5.5 v, v out = 1.1 v, f sw = 3.3 mhz 65 ns maximum duty cycle 100 % enable characteristics en input high threshold 1.2 v en input low threshold 0.4 v en input leakage current v en = 0 v, 5.5 v ?1 +0.01 +1 a oscillator frequency 2.7 3.0 3.3 mhz soft start period c out = 4.7 f 300 s thermal characteristics thermal shutdown threshold 150 c thermal shutdown hysteresis 20 c 1 limits in bold face type apply over the full operating ambient temperature range ?40c ta +85c 2 open-loop data. refer to the typical performance characteristics for closed loop data 3 v out (min) must be greater than (.19).
adp2108 preliminary technical data rev. pra | page 4 of 15 absolute maximum ratings table 2. parameter rating vin, en ?0.3 v to +6 v fb, sw to pgnd ?0.3 v to (v in + 0.2 v) operating ambient temperature range C40c to +85c operating junction temperature range C40c to +125c storage temperature range C65c to +150c lead temperature range tbd soldering (10 sec) 300c vapor phase (60 sec) 215c infrared (15 sec) 220c esd human body model 2000 v esd charged device model 500 v esd machine model 100 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, ja is specified for device soldered on a circuit board single layer for surface-mount packages. table 3. thermal resistance package type ja unit 5-ball wlcsp 200 c/w maximum power dissipation 200 mw esd caution
preliminary technical data adp2108 rev. pra | page 5 of 15 pin configuration and function descriptions vin gnd sw en fb top view (ball side down) not to scale 07375-002 1 a b c 2 bal l a1 indicator figure 2. 5-ball wclsp pin configuration table 4. pin function descriptions pin no. mnemonic description 1 vin power source input. vin is the source of the pfet high-side switch. bypass vin to gnd with a 2.2 f or greater capacitor as close to the adp2108 as possible. 2 gnd ground. connect all the input and output capacitors to gnd. 3 en enable input. drive en high to turn on the adp2108. drive en low to turn it off and reduce the input current to 0.1 a. 4 fb feedback input of the error amplifier. connect fb to the output of the switching regulator. 5 sw switch node output. sw is the drain of the p-channel mosfet switch and n-channel synchronous rectifier. connect the output lc filter between sw and the output voltage.
adp2108 preliminary technical data rev. pra | page 6 of 15 typical performance characteristics v in = 3.6 v, t a = 25c, v en = v in, unless otherwise noted 07375-008 ch1 100mv ch2 200ma c h4 2v m 4s a ch1 2mv 1 4 2 t 49.8% figure 3 pfm operation at iload = 40ma 07375-009 ch1 20mv ch3 2v c h4 2v m 100s a ch1 ?8.40mv 1 4 3 t 45.2% figure 4 line transient fall iload = 100ma, vin = 3.6v C 4.2v 07375-010 ch1 20mv ch3 2v c h4 2v m 100s a ch3 3.96mv t 45.2% 4 3 1 figure 5 line transient riseiload = 100ma, vin = 3.6v C 4.2v 07375-011 ch1 1v ch2 500ma ch3 5v ch4 2v m 40s a ch3 4.1v 1 2 4 3 t 12% figure 6 start up waveform iload = 10ma 07375-012 ch1 1v ch2 500ma ch3 5v c h4 2v m 40s a ch3 4.1v 1 2 4 3 t 12% figure 7start up waveform iload = 600ma 07375-013 ch1 50mv ch2 500ma c h4 2v m 200ns a ch4 2.08v 1 4 2 t ?12ns figure 8 pwm operation at iload = 150ma
preliminary technical data adp2108 rev. pra | page 7 of 15 theory of operation pgnd slope compensation current limit pwm/ pfm control soft-start reference 0.5v fb vin sw g m error a mp zero cross comparator current sense amp 3mhz oscillator thermal shutdown driver and antishoot through en adp2108 07375-001 figure 9. functional block diagram the adp2108 is a step-down dc-to-dc converter that uses a fixed frequency and high speed current mode architecture. the high 3 mhz switching frequency and tiny 5-ball, wlcsp package allow for a small step-down dc-to-dc converter solution. the adp2108 operates with an input voltage from 2.3 v to 5.5 v and regulate an output voltage down to 0.8 v. output voltage options are 3.3 v, 3.0 v, 2.5 v, 2.3 v, 1.8 v, 1.5 v, 1.3 v, 1.2 v, 1.1 v, and 1.0 v. control scheme the adp2108 operates with a fixed frequency, currentmode pwm control architecture at medium to high loads for high efficiency, but shift to a variable frequency pfm control scheme at light loads for lower quiescent current. when operating in fixed frequency pwm mode, the duty cycle of the integrated switches is adjusted to regulate the output voltage, but when operating in pfm mode at light loads, the switching frequency is adjusted to regulate the output voltage. the adp2108 operate in the pwm mode only when the load current is greater than the pulse-skipping threshold current. at load currents below this value, the converter smoothly transitions to the pfm mode of operation. pwm operation in pwm mode, the adp2108 operates at a fixed frequency of 3 mhz set by an internal oscillator. at the start of each oscillator cycle, the p-channel mosfet switch is turned on, putting a positive voltage across the inductor. current in the inductor increases until the current sense signal crosses the peak inductor current level that turns off the p-channel mosfet switch and turns on the n-channel mosfet synchronous rectifier. this puts a negative voltage across the inductor, causing the inductor current to decrease. the synchronous rectifier stays on for the rest of the cycle, unless the inductor current reaches zero, which also causes the zero- crossing comparator to turn off the n-channel mosfet. pfm operation the adp2108 has a smooth transitions to the variable frequency pfm mode of operation when the load current decreases below the pulse skipping threshold current, switching only as necessary to maintain the output voltage within regulation. when the output voltage dips below regulation, the adp2108 enter pwm mode for a few oscillator cycles to increase the output voltage back to regulation. during the wait time between bursts, both power switches are off, and the output capacitor supplies the entire load current. because the output voltage dips and recovers occasionally, the output voltage ripple in this mode is larger than the ripple in the pwm mode of operation.
adp2108 preliminary technical data rev. pra | page 8 of 15 pulse skipping threshold the output current at which the adp2108 transitions from variable frequency pfm control to fixed frequency pwm control is called the pulse-skipping threshold. the pulse skipping threshold has been optimized for excellent efficiency over all load currents. slope compensation to avoid subharmonic oscillations, slope compensation is introduced to stabilize the adp2108 internal current loop when operating beyond a 50% duty cycle. it is implemented by summing a fixed scaled voltage ramp to the current sense signal during the on time of the p-channel mosfet switch. the value of the compensation ramp is important because it is required to determine the minimum inductor to prevent subharmonic oscillations on the selected output voltage. table 5. slop compensation rate o utput voltage slope compensation rate 1.1 1.8 a/s 1.8 3 a/s 3.3 5.4 a/s product features enable/shutdown the adp2108 starts operation with soft start when the en pin is toggled from logic low to logic high. pulling the en pin low forces the device into shutdown mode, reducing the shutdown current below 1 la. short-circuit protection the adp2108 includes frequency foldback to prevent output current runaway on a hard short. when the voltage at the feedback pin falls below 0.3 v, indicating the possibility of a hard short at the output, the switching frequency is reduced to 1/4 of the internal oscillator frequency. the reduction in the switching frequency gives more time for the inductor to discharge, preventing a runaway of output current. undervoltage lockout to protect against battery discharge, undervoltage lockout circuitry is integrated on the adp2108. if the input voltage drops below the 2.15 v undervoltage lockout (uvlo) threshold, the adp2108 shut down, and both the power switch and synchronous rectifier turns off. when the voltage rises again above the uvlo threshold, the soft start period is initiated, and the part is enabled. thermal protection in the event the adp2108 junction temperatures rise above 150c, the thermal shutdown circuit turns off the converter. extreme junction temperatures can be the result of high current operation, poor circuit board design, and/or high ambient temperature. a 30c hysteresis is included so when thermal shutdown occurs, the adp2108 does not return to operation until the on-chip temperature drops below 120c. when coming out of thermal shutdown, soft start is initiated. soft start the adp2108 has an internal soft start function that ramps the output voltage in a controlled manner upon startup, therefore limiting the inrush current. this prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. current limit the adp2108 have protection circuitry to limit the direction and amount of current to 1200 ma flowing through the power switch and synchronous rectifier. the positive current limit on the power switch limits the amount of current that can flow from the input to the output, and the negative current limit on the synchronous rectifier prevents the inductor current from reversing direction and flowing out of the load.
preliminary technical data adp2108 rev. pra | page 9 of 15 applications external component selection the external component selection for the adp2108 application circuit shown in figure 1 is dependent on input voltage, output voltage, and load current requirements. additionally, trade-offs between performance parameters like efficiency and transient response can be made by varying the choice of external components. selecting the inductor the high frequency switching of the adp2108 allows the selection of small chip inductors. the inductor value effects the transition between cfm to pfm, efficiency, output ripple and current limit values. the inductor current ripple is calculated using the following equation: lfv vvv i swin out in out l ? =? )( where: f sw is the switching frequency (3 mhz typical). l is the inductor value. the dc resistance (dcr) value of the selected inductor affects efficiency but a decrease in this value typically means an increase in root mean square (rms) with losses in the core and skin. as a minimum requirement, the dc current rating of the inductor is to be equal to the maximum load current plus half of the inductor current ripple as shown by the following equation: ) 2 ( )( l max load pk i ii ? + = theadd2dpwvvagcamdp2wdlcdsnmwycqig vendor model dimensions dcr murata lqm21pn1r0m 2.0 mm x 1.25 mm x 0.5mm 190 mp murata lqm31pn1r0m 3.2 mm x 1.6mm x 0.95mm 120 mp murata lqm2hpn1r0m 2.5 mm x 2.0mm x 0.95mm 90 mp fdk mipsa2520d1r 2.5 mm x 2.0 mm x 1.0mm 100 mp output capacitor output capacitance is required to minimize the voltage overshoot and ripple present on the output. capacitors with low equivalent series resistance (esr) values produce the lowest output ripple and capacitors such as x5r dielectric are to be used. y5v capacitors are not to be used due to their variation in capacitance over temperature, which does not suit this application. becuase esr is important the capacitor is to be selected using the following equation: l ripple cout i v e sr ? w here v ripple is peak-to-peak output voltage ripple and esr cout is the esr of the chosen capacitor. the output capacitor can be chosen use the following: ripple sw in out vlf v c 2)2( out sw l vf i c out ? ? 8 i ncreasing the output capacitor has no effect on stability so it can be increased to reduce output ripple and enhance load transient response. when choosing this value it is also important to account for the loss of capacitance due to output voltage dc bias. theadk2dpwvvagcamd,2kwod-tttyfcqigd vendor type model case size voltage rating murata x5r grm188r60j475 0603 6.3v taiyo yuden x5r jmk107bj475 0603 6.3v tdk x5r c1608x5r0j475 0603 6.3v input capacitor an input capacitor is required to reduce input voltage ripple and is to be placed as close as possible to the vin pin. as with the output capacitor, a low esr capacitor is recommended to help to minimize input voltage ripple. in out inout max load cin v vvv ii )( )( ? e fficiency efficiency is defined as the ratio of output power to input power. the high efficiency of the adp2108 has two distinct advantages. first, only a small amount of power is lost in the dc- to-dc converter package that reduces thermal constraints. in addition, high efficiency delivers the maximum output power for the given input power, extending battery life in portable applications. the overall efficiency of the adp2108 can be calculated by adding together the power losses caused by the power switches and inductor. power switch conduction losses power switch conduction losses are caused by the flow of output current through the p-channel power switch and the n-channel synchronous rectifier, which have internal resistances (r ds(on) ) associated with them. the amount of power loss can be approximated by 2 _)( _)( _ ))1( ( out nonds ponds cond sw id rd r p ? + =
adp2108 preliminary technical data rev. pra | page 10 of 15 where d = v out /v in . the internal resistance of the power switches increases with temperature but decreases with higher input voltage. inductor losses inductor conduction losses are caused by the flow of current through the inductor, which has an internal dcr associated with it. larger sized inductors have smaller dcr, which may decrease inductor conduction losses. inductor core losses are related to the magnetic permeability of the core material. because the adp2108 is a high switching frequency dc-to-dc converter, shielded ferrite core material is recommended for its low core losses and low emi. the total amount of inductor power loss can be calculated by lossescore idcrp out l += 2 switching losses switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. each time a power device gate is turned on and turned off, the driver transfers a charge pq from the input supply to the gate and then from the gate to ground. the amount of power loss is calculated by sw i n ngate pgate sw fvccp += 2 ) ( _ _ w here: c gate_p is the gate capacitance of the internal high-side switch. c gate_n is the gate capacitance of the internal low-side switch. ngate pgate cc _ _ + 100pf f s w i s the switching frequency. transition losses transition losses occur because the p-channel switch cannot turn on or turn off instantaneously. in the middle of an lx node transition, the power switch provides all the inductor current. the source to drain voltage of the power switch is half the input voltage, resulting in power loss. transition losses increase with load current and input voltage and occur twice for each switching cycle. the amount of power loss is calculated by sw fr out in tran fttivp += )(2/ where: t r is the rise time of the lx node. t f is the fall time of the lx node. t r and t f are both approximately 2ns. lytpsawa7i0nf,tpagfi0na in most applications, the adp2108 does not dissipate a lot of heat, due to its high efficiency. however, in applications with maximum loads at high ambient temperature, low supply voltage, and high duty cycle, the heat dissipated in the package is great enough that it may cause the junction temperature of the die to exceed the maximum junction temperature of 125c. once the junction temperature exceeds 150c, the converter goes into thermal shutdown. it recovers only after the junction temperature has decreased to below 120c to prevent any permanent damage. therefore, thermal analysis for the chosen application solution is very important to guarantee reliable performance over all conditions. the junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to power dissipation, shown in the following equation: t j = t a + t r where: t j is the junction temperature. t a is the ambient temperature. t r is the rise in temperature of the package due to power dissipation to it. the rise in temperature of the package is directly proportional to the power dissipation in the package. the proportionality constant for this relationship is defined as the thermal resistance from the junction of the die to the ambient temperature, as shown in the following equation: djar pt = where: t r is the rise of temperature of the package. ja is the thermal resistance from the junction of the die to the ambient temperature of the package. p d is the power dissipation in the package. .
preliminary technical data adp2108 rev. pra | page 11 of 15 capacitor selection use any good quality ceramic capacitors with the adp1208 as long as they meet the minimum capacitance and maximum esr requirements. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended for best performance. y5v and z5u dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. the following equation can be used to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c bias (1 C tempco) 1(1 C tol) where: c bias is the effective capacitance at the operating voltage. tempco is the worst-case capacitor temperature coefficient. tol is the worst-case component tolerance. in this example, the worst-case temperature coefficient ( tempco ) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor ( tol ) is assumed to be 10%, and c bias is 4.02165 lf at 1.8 v from the graph in figure 10. substituting these values in equation yields c eff = 4.02165 lf (1 C 0.15) (1 C 0.1) = 3.0762 lf to guarantee the performance of the adp2108, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors are evaluated for each application. 0 1 2 3 4 5 6 0 1 2 3 4 5 6 dc bias voltage (v) capacitance (uf) figure 9 C typical capacitor performance
adp2108 preliminary technical data rev. pra | page 12 of 15 pcb layout guidelines poor layout can affect the adp2108 performance causing electromagnetic interference (emi) and electromagnetic compatibility (emc) performance, ground bounce, and voltage losses. poor layout can also affect regulation and stability. a good layout is implemented using the following rules: ? place the inductor, input capacitor and output capacitor close to the ic using short tracks. these components carry high switching frequencies and large tracks act like antennas. ? route the output voltage path away from the inductor and sw node to minimize noise and magnetic interference. ? maximize the size of ground metal on the component side to help with thermal dissipation. ? use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes.
preliminary technical data adp2108 rev. pra | page 13 of 15 evaluation board v out gnd out v out adp2108 tb3 tb4 c out 4.7f l1 1h u1 1b c2 a1 v in c1 a2 gnd 2 c in 4.7f 07375-004 v in en en vin sw fben tb1 tb2 gnd in tb5 figure 10. 07375-005 figure 11. recommended top layer 07375-006 figure 12. recommended bottom layer
adp2108 preliminary technical data rev. 0 | page 14 of 15 outline dimensions seating plane 0.50 ref 0.87 0.37 0.36 0.35 0.17 0.14 0.12 0.21 0.50 0.20 0.50 0.23 0.18 0.14 bottom view (ball side up) 0.94 0.90 0.86 1.33 1.29 1.25 top view (ball side down) ball 1 identifier a 12 b c 101607-a figure 13. 5-ball wafer level chip scale package [wlcsp] (cb-5-1) dimensions shown in millimeters ordering guide model temperature range output voltage (v) package description package option branding adp2108acbz - 1.0 C r7 1 C40c to +85c 1.0 5-ball wlcsp cb la6 adp2108acbz - 1.1 C r7 1 C40c to +85c 1.1 5-ball wlcsp cb la7 adp2108acbz - 1.2 C r7 1 C40c to +85c 1.2 5-ball wlcsp cb la8 adp2108acbz - 1.3 C r7 1 C40c to +85c 1.3 5-ball wlcsp cb la9 adp2108acbz - 1.5 C r7 1 C40c to +85c 1.5 5-ball wlcsp cb laa adp2108acbz - 1.8 C r7 1 C40c to +85c 1.8 5-ball wlcsp cb lad adp2108acbz - 1.82 C r7 1 C40c to +85c 1.82 5-ball wlcsp cb lae adp2108acbz - 2.3 C r7 1 C40c to +85c 2.3 5-ball wlcsp cb laf adp2108acbz - 2.5 C r7 1 C40c to +85c 2.5 5-ball wlcsp cb lag adp2108acbz C 3.0 C r7 1 C40c to +85c 3.0 5-ball wlcsp cb adp2108acbz - 3.3 C r7 1 C40c to +85c 3.3 5-ball wlcsp cb lah 1 z = rohs compliant part.
preliminary technical data adp2108 rev. 0 | page 15 of 15 pr07375-0-5/08(pra) not es

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